1. Technical Field
The present invention relates to a method of fabricating semiconductor devices. More specifically, the present invention is directed to a method of fabricating non-volatile memory devices of a split gate type.
2. Discussion of Related Art
As electrical devices become pocket-sized and portable, non-volatile memory devices are needed to preserve stored information when the device loses power. FLASH memory devices are non-volatile and data can further be electrically programmed and erased. The FLASH memory devices are classified as stack-gate type and slit-gate type memory devices.
A stack-gate type FLASH memory device comprises a floating gate and a control gate, which are sequentially stacked. In addition, the stack-gate type FLASH memory uses a channel hot electron injection and Fowler-Nordheim tunneling to program and erase memory. An advantage of the stack-gate type FLASH memory is that it can be highly integrated. However, a disadvantage of a stack-gate type FLASH memory is that it over-erases and it turns on unselected cell transistors. A split-gate type FLASH memory device includes a control gate disposed over a channel to control the on and off state of the channel to prevent the over-erasing problem.
FIGS. 1-4 are cross-sectional views for illustrating a conventional method of fabricating a split gate type memory device.
Referring to FIG. 1, a device isolation layer (not shown) is formed to define an active region in a predetermined region of a substrate 10. A lower conductive layer parallel to the active region is formed on a substrate with the device isolation layer. Therefore, a top surface of the device isolation layer is exposed between two adjoining lower conductive layers.
A sacrificial pattern 88, which is preferably a silicon nitride, is formed on the lower conductive layer. The sacrificial pattern 88 includes a trench that crosses over the active region and exposes a top portion of the lower conductive layer. Mask spacers 30 are formed on inner sidewalls of the trench. Then, the lower conductive layer is etched using the mask spacers 30 as an etch mask. Thus, a lower conductive pattern 20 is formed under the mask spacers 30 and the sacrificial pattern 88, and a portion of the substrate between the spacers 30 is exposed. In this case, the mask spacers 30 have curved sidewalls like a conventional spacer. Therefore, the mask spacers 30 become narrower from a bottom portion to a top portion of the spacers.
An impurity region serving as a source “s” is formed in the exposed portion of the substrate 10. Then, insulation spacers are formed on sidewalls of the lower conductive pattern 20. Next, a plug conductive layer 40, which is connected to the source “s,” is formed by filling a gap region formed between the mask spacers 30 and the insulation spacers.
Referring to FIGS. 2 and 3, the plug conductive layer 40 is planarized by etching until a top portion of the sacrificial pattern 88 is exposed, thereby forming a source plug 45 that fills the gap region. A silicon oxide layer is formed on the source plug 45, and the exposed sacrificial pattern 88 is removed. Thus, the lower conductive pattern 20 is exposed beside the mask spacers 30. Next, the exposed lower conductive pattern 20 is etched to form floating gates 25 under the mask spacers 30. Then, oxide layers are formed on the sidewalls of the floating gate 25. Next, an upper conductive layer 50 is conformally formed to a thickness0 to cover the entire resultant structure.
The upper conductive layer 50 is planarized by etching to expose the mask spacers 30, thereby forming an upper conductive pattern beside the mask spacers 30. The upper conductive pattern is patterned to form control gates 55 on the sidewalls of the mask spacers 30. Next, impurity regions are formed in a substrate beside the control gates 55. The impurity regions serve as a drain “d.”
The control gates 55 comprise a word line of cell transistors. Therefore, as the control gate 55 becomes thinner, resistance of the word line increases and operation speed of the device decreases. Thus, the upper conductive layer 50 should be planarized by etching to have a sufficient height for the control gate 55 to decrease resistance of the word line and to maintain operational speed of a device. For this, the upper conductive layer 50 must be thick and the mask spacers 30 must be high. Since the height of the mask spacers 30 depend on the height of the sacrificial pattern 88, the sacrificial pattern 88 should be formed thicker than the predetermined height of the mask spacers 30. However, forming an excessively thick silicon nitride is not preferred because the sacrificial pattern 88 is formed at a high temperature. Thus, the thermal budget may cause the diffusion of impurities implanted into the source “s” to occur during the formation of the sacrificial pattern 88.
In addition, as the height of the mask spacers 30 decreases, the upper width I1 of FIG. 2 becomes narrower. This is due to the shape of the mask spacer, which becomes narrower from the bottom to the top thereof. In addition, an interconnection 70 connected to the source plug 45 is also connected to the control gates 55 and causes a short 99. As illustrated in FIG. 4, as the height of the mask spacer 30 increases, the upper width I2 of the etched mask spacer 30 also increases. Thus, short circuiting may be prevented.
Further, using silica and ceria as a slurry, a chemical mechanical polishing process is used as a planarizing etching process for forming the source plug 45. In this case, a plug conductive layer 40 of polysilicon and a sacrificial pattern 88 of silicon nitride are successively etched during the planarizing process, resulting in a non-uniform etch.